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PDF NCV47821 Data sheet ( Hoja de datos )
| Número de pieza | NCV47821 | |
| Descripción | 3.3V to 20V Adjustable Dual LDO | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NCV47821
3.3 V to 20 V Adjustable Dual
LDO with Adjustable Current
Limit and Diagnostic Features
The NCV47821 dual channel LDO regulator with 200 mA per
channel is designed for use in harsh automotive environments. The
device has a high peak input voltage tolerance and reverse input voltage,
reverse bias, overcurrent and overtemperature protections. The
integrated current sense feature (adjustable by resistor connected to
CSO pin for each channel) provides diagnosis and system protection
functionality. The CSO pin output current creates voltage drop across
CSO resistor which is proportional to output current of each channel.
Extended diagnostic features in OFF state are also available and
controlled by dedicated input and output pins.
Features
• Adjustable Outputs: 3.3 V to 20 V ±3% Output Voltage
• Output Current per Channel: up to 200 mA
• Two Independent Enable Inputs (3.3 V Logic Compatible)
• Adjustable Current Limits: up to 300 mA
• Protection Features:
♦ Current Limitation
♦ Thermal Shutdown
♦ Reverse Input Voltage and Reverse Bias Voltage
• Diagnostic Features:
♦ Short To Battery (STB) and Open Load (OL) in OFF State
♦ Internal Components for OFF State Diagnostics
♦ Open Collector Flag Output
• AEC−Q100 Grade 1 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
www.onsemi.com
14
1
TSSOP−14
Exposed Pad
CASE 948AW
MARKING
DIAGRAM
14
NCV4
7821
ALYWG
G
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
Typical Applications
• Audio and Infotainment System
• Active Safety System
Cin
1 μF
Vin
EN1
Diagnostic Enable Input
DE
Diagnostic Channel Select Input
CS
Vout1
ADJ1
CSO1
CCSO1
NCV47821
(Dual LDO )
1 μF
EF
Vout2
EN2
GND
ADJ2
CSO2
CCSO2
1 μF
R11
To A /D
RCSO1 R12
Cb1*
Cout1
10 μF
Error Flag Output (Open Collector)
R21
To A /D
RCSO2 R22
Cb2*
Cout2
10 μF
Cb1* and Cb2* are optional for stability with ceramic output capacitors
Figure 1. Application Schematic
(See Application Section for More Details)
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 1
1
Publication Order Number:
NCV47821/D
1 page  
NCV47821
Table 6. ELECTRICAL CHARACTERISTICS Vin = 13.5 V, VEN1,2 = 3.3 V, VDE = 0 V, RCSO1,2 = 0 W, CCSO1,2 = 1 mF, Cin = 1 mF,
Cout1,2 = 10 mF, Min and Max values are valid for temperature range −40°C v TJ v +150°C unless noted otherwise and are guaranteed
by test, design or statistical correlation. Typical values are referenced to TJ = 25°C (Note 8)
Parameter
Test Conditions
Symbol Min Typ Max Unit
REGULATOR OUTPUTS
Output Voltage (Accuracy %) (Note 9)
Vin = Vin_min to 40 V
Iout1,2 = 5 mA to 200 mA
Vout1,2
%
−3 − +3
Line Regulation (Note 9)
Vin = Vin_min to (Vout_nom1,2 + 20 V)
Iout1,2 = 5 mA
Regline1,2
−
%
0.1 1.0
Load Regulation
Vin = (Vout_nom1,2 + 8.5 V)
Iout1,2 = 5 mA to 200 mA
Regload1,2
−
%
0.4 1.4
Dropout Voltage (Note 10)
Vout_nom1,2 = 5 V, Iout1,2 = 200 mA
VDO1,2 = Vin − Vout1,2
VDO1,2 − 250 500 mV
DISABLE AND QUIESCENT CURRENTS
Disable Current
VEN1,2 = 0 V, Vout_nom1,2 = 5 V,
−40°C v TJ v +125°C
IDIS − 0.1 10 mA
Quiescent Current, Iq = Iin − (Iout1 +Iout2) Iout1 = Iout2 = 500 mA, Vin = (Vout_nom + 8.5 V)
Quiescent Current, Iq = Iin – (Iout1 +Iout2) Iout1 = Iout2 = 200 mA, Vin = (Vout_nom + 8.5 V)
CURRENT LIMIT PROTECTION
Iq
Iq
− 0.6 1.0 mA
− 15.5 25 mA
Current Limit
Vout1,2 = 0.9 x Vout_nom1,2
Vin = (Vout_nom1,2 + 8.5 V)
ILIM1,2
300
−
− mA
PSRR & NOISE
Power Supply Ripple Rejection (Note 11) f = 100 Hz, 0.5 Vp−p1,2
Output Noise Voltage (Note 11)
f = 10 Hz to 100 kHz, Cb1,2 = 10 nF
ENABLE
PSRR1,2
−
75
− dB
Vn1,2
− 137
− mVrms
Enable Input Threshold Voltage
Logic Low (OFF)
Logic High (ON)
Vout1,2 v 0.1 V
Vout1,2 w 0.9 x Vout_nom1,2 (Vout_nom1,2 = 5 V)
Vth(EN1,2)
0.99
−
1.8
1.9
−
2.31
V
Enable Input Current
Turn On Time
from Enable ON to 90 % of Vout
VEN1,2 = 3.3 V, Vout_nom1,2 = 5 V
Iout1,2 = 100 mA, Cb1,2 = 10 nF,
Rn1 = 82 kW, Rn2 = 27 kW
IEN1,2
2
8 20 mA
ton ms
− 1.7 −
OUTPUT CURRENT SENSE
CSO Voltage Level at Current Limit
Vout1,2 = 0.9 x Vout_nom1,2,
(Vout_nom1,2 = 5 V) RCSO1,2 = 1 kW
VCSO_Ilim1,2 2.448
(−4%)
2.55
2.652
(+4%)
V
CSO Transient Voltage Level
CCSO1,2 = 4.7 mF, RCSO1,2 = 1 kW
Iout1,2 pulse from 10 mA to 300 mA, tr = 1 ms
VCSO1,2
−
V
− 3.3
Output Current to CSO Current Ratio
(Note 12)
VCSO1,2 = 2 V, Iout1,2 = 10 mA to 300 mA
(Vout_nom1,2 = 5 V)
Iout1,2/ − 100 −
ICSO1,2 (−5%)
(+5%)
−
CSO Current at no Load Current
VCSO1,2 = 0 V, Iout1,2 = 0 mA,
(Vout_nom1,2 = 5 V)
ICSO_off1,2
−
−
10 mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TA [ TJ. Low duty
cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
9. Minimum input voltage Vin_min is 4.4 V or (Vout_nom1,2 + 1 V) whichever is higher. Vout_nom1,2 measured at ADJ1,2 pin due to excluding
Rn1 and Rn2 accuracy.
10. Measured when the output voltage Vout1,2 has dropped by 2% of Vout_nom1,2 from the nominal valued obtained at Vin = Vout1,2 + 8.5 V.
11. Values based on design and/or characterization.
12. Not guaranteed in dropout.
www.onsemi.com
5
5 Page 
NCV47821
APPLICATIONS INFORMATION
Circuit Description
The NCV47821 is an integrated dual low dropout
regulator that provides a regulated voltage at 200 mA to each
output. It is enabled with an input to the enable pin. The
regulator voltage is provided by a PNP pass transistor
controlled by an error amplifier with a bandgap reference,
which gives it the lowest possible dropout voltage. The
output current capability of the LDO is 200 mA per output
and the base drive quiescent current is controlled to prevent
oversaturation when the input voltage is low or when the
output is overloaded. The integrated current sense feature
provides diagnosis and system protection functionality. The
current limit of the device is adjustable by resistor connected
to CSO pin. Voltage on CSO pin is proportional to output
current. The regulator is protected by both current limit and
thermal shutdown. Thermal shutdown occurs above 150°C
to protect the IC during overloads and extreme ambient
temperatures.
Regulator
The error amplifier compares the reference voltage to a
sample of the output voltage (Vout1,2) and drives the base of
a PNP series pass transistor via a buffer. The reference is a
bandgap design to give it a temperature stable output.
Saturation control of the PNP is a function of the load current
and input voltage. Oversaturation of the output power
device is prevented, and quiescent current in the ground pin
is minimized.
Regulator Stability Considerations
The input capacitor (Cin) is necessary to stabilize the input
impedance to avoid voltage line influences. The output
capacitor (Cout1,2) helps determine three main
characteristics of a linear regulator: startup delay, load
transient response and loop stability. The capacitor value
and type should be based on cost, availability, size and
temperature constraints. The aluminum electrolytic
capacitor is the least expensive solution, but, if the circuit
operates at low temperatures (−25°C to −40°C), both the
value and ESR of the capacitor will vary considerably. The
capacitor manufacturer’s data sheet usually provides this
information. The value for the output capacitor Cout1,2,
shown in Figure 1 should work for most applications; see
also Figure 16 for output stability at various load and Output
Capacitor ESR conditions. Stable region of ESR in
Figure 16 shows ESR values at which the LDO output
voltage does not have any permanent oscillations at any
dynamic changes of output load current. Marginal ESR is
the value at which the output voltage waving is fully damped
during four periods after the load change and no oscillation
is further observable.
ESR characteristics were measured with ceramic
capacitors and additional series resistors to emulate ESR.
Low duty cycle pulse load current technique has been used
to maintain junction temperature close to ambient
temperature.
Calculating Bypass Capacitor
If improved stability (reducing output voltage ringing
during transients) is demanded, connect the bypass
capacitor Cb1,2 between Adjustable Input pin and Vout1,2 pin
according to Applications circuit at Figure 1. Parallel
combination of bypass capacitor Cb1,2 with the feedback
resistor Rn1 contributes in the device transfer function as an
additional zero and affects the device loop stability,
therefore its value must be optimized. Attention to the
Output Capacitor value and its ESR must be paid. See also
Stability in High Speed Linear LDO Regulators Application
Note, AND8037/D for more information. Optimal value of
bypass capacitor is given by following expression
Cbn + 2
1
p fz
Rn1 (F)
(eq. 1)
where
Rn1 the upper feedback resistor
fz the frequency of the zero added into the device
transfer function by Rn1 and Cb1 external
components.
Set the Rn1 resistor according to output voltage requirement.
Chose the fz with regard on the output capacitance Cout1,2,
refer to the table below.
Cout1,2 (mF)
fZ range (kHz)
10
max 19
22
max 19
47
N/A*
100
N/A*
NOTE: * For Cout1,2 = 47 mF and higher, Cb1,2 capacitors are not
needed for stability improvement. Cb1,2 capacitors are
useful for reduction start up overshoot and noise
reduction. See electrical characteristic table.
Ceramic capacitors and its part numbers listed bellow
have been used as low ESR output capacitors Cout1,2 from
the table above to define the frequency ranges of additional
zero required for stability:
GRM31CR71C106KAC7 (10 mF, 16 V, X7R, 1206)
GRM32ER71C226KE18 (22 mF, 16 V, X7R, 1210)
GRM32ER61C476ME15 (47 mF, 16 V, X5R, 1210)
GRM32ER60J107ME20 (100 mF, 6.3 V, X5R, 1210)
Enable Inputs
An enable pin is used to turn a channel on or off. By
holding the pin down to a voltage less than 0.99 V, the output
of the channel will be turned off. When the voltage on the
enable pin is greater than 2.31 V, the output of the channel
will be enabled to power its output to the regulated output
voltage. The enable pins may be connected directly to the
input pin to give constant enable to the output channel.
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11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet NCV47821.PDF ] | |
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