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NB3V60113G PDF даташит

Спецификация NB3V60113G изготовлена ​​​​«ON Semiconductor» и имеет функцию, называемую «1.8V Programmable OmniClock Generator».

Детали детали

Номер произв NB3V60113G
Описание 1.8V Programmable OmniClock Generator
Производители ON Semiconductor
логотип ON Semiconductor логотип 

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NB3V60113G Даташит, Описание, Даташиты
NB3V60113G
1.8 V Programmable
OmniClock Generator
with Single Ended (LVCMOS) and Differential
(LVDS/HCSL) Outputs
The NB3V60113G, which is a member of the OmniClock family, is
a one−time programmable (OTP), low power PLL−based clock
generator that supports any output frequency from 8 kHz to 200 MHz.
The device accepts fundamental mode parallel resonant crystal or a
single ended (LVCMOS) reference clock as input. It generates either
three single ended (LVCMOS) outputs, or one single ended output and
one differential (LVDS/HCSL) output. The output signals can be
modulated using the spread spectrum feature of the PLL
(programmable spread spectrum type, deviation and rate) for
applications demanding low electromagnetic interference (EMI).
Using the PLL bypass mode, it is possible to get a copy of the input
clock on any or all of the outputs. The device can be powered down
using the Power Down pin (PD#). It is possible to program the internal
input crystal load capacitance and the output drive current provided by
the device. The device also has automatic gain control (crystal power
limiting) circuitry which avoids the device overdriving the external
crystal.
www.onsemi.com
WDFN8
CASE 511AT
MARKING DIAGRAM
1
V0MG
G
V0 = Specific Device Code
M = Date Code
G = Pb−Free Device
(Note: Microdot may be in either location)
Features
Member of the OmniClock Family of Programmable Clock
Generators
Operating Power Supply: 1.8 V ± 0.1 V
I/O Standards
Inputs: LVCMOS, Fundamental Mode Crystal
Outputs: LVCMOS
Outputs: LVDS and HCSL
3 Programmable Single Ended (LVCMOS) Outputs
from 8 kHz to 200 MHz
1 Programmable Differential Clock Output up to
200 MHz
Input Frequency Range
Crystal: 3 MHz to 50 MHz
Reference Clock: 3 MHz to 200 MHz
Configurable Spread Spectrum Frequency Modulation
Parameters (Type, Deviation, Rate)
Programmable Internal Crystal Load Capacitors
Programmable Output Drive Current for Single Ended
Outputs
ORDERING INFORMATION
See detailed ordering and shipping information on page 19 of
this data sheet.
Power Saving mode through Power Down Pin
Programmable PLL Bypass Mode
Programmable Output Inversion
Programming and Evaluation Kit for Field
Programming and Quick Evaluation
Temperature Range −40°C to 85°C
Packaged in 8−Pin WDFN
These are Pb−Free Devices
Typical Applications
eBooks and Media Players
Smart Wearables, Portable Medical and Industrial
Equipment
Set Top Boxes, Printers, Digital Cameras and
Camcorders
© Semiconductor Components Industries, LLC, 2016
January, 2016 − Rev. 2
1
Publication Order Number:
NB3V60113G/D









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NB3V60113G Даташит, Описание, Даташиты
NB3V60113G
BLOCK DIAGRAM
VDD PD#
XIN/CLKIN
Crystal
XOUT
Crystal/Clock Control
Clock Buffer/
Crystal
Oscillator and
AGC
PLL Block
Phase
Detector
Configuration
Memory
Frequency
and SS
Charge
Pump
VCO
Feedback
Divider
Output control
Output
Divider
Output
Divider
CMOS/
Diff
buffer
CMOS /
Diff
buffer
Output
Divider
CMOS
buffer
PLL Bypass Mode
GND
Notes:
1. CLK0 and CLK1 can be configured to be one of LVDS or HCSL output, or two single−ended LVCMOS outputs.
2. Dotted lines are the programmable control signals to internal IC blocks.
3. PD# has internal pull down resistor.
Figure 1. Simplified Block Diagram
PIN FUNCTION DESCRIPTION
CLK0
CLK1
CLK2
XIN/CLKIN 1
XOUT 2
PD# 3
GND 4
NB3V60113G
8 CLK2
7 VDD
6 CLK1
5 CLK0
Figure 2. Pin Connections (Top View) – WDFN8
www.onsemi.com
2









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NB3V60113G Даташит, Описание, Даташиты
NB3V60113G
Table 1. PIN DESCRIPTION
Pin No.
Pin Name Pin Type
1
XIN/CLKIN
Input
2
XOUT
Output
3 PD# Input
4
GND
Ground
5
CLK0
SE/DIFF
output
6
CLK1
SE/DIFF
output
7
VDD
Power
8
CLK2
SE
output
Description
3 MHz to 50 MHz crystal input connection or an external single−ended reference input
clock between 3 MHz and 200 MHz
Crystal output. Float this pin when external reference clock is connected at XIN
Asynchronous LVCMOS input. Active Low Master Reset to disable the device and set
outputs Low. Internal pull−down resistor. This pin needs to be pulled High for normal op-
eration of the chip.
Power supply ground
Supports 8 kHz to 200 MHz Single−Ended (LVCMOS) signals or Differential (LVDS/
HCSL) signals. Using PLL Bypass mode, the output can also be a copy of the input clock.
The single ended output will be LOW and differential outputs will be complementary LOW/
HIGH until the PLL has locked and the frequency has stabilized.
Supports 8 kHz to 200 MHz Single−Ended (LVCMOS) signals or Differential (LVDS/
HCSL) signals. Using PLL Bypass mode, the output can also be a copy of the input clock.
The single ended output will be LOW and differential outputs will be complementary LOW/
HIGH until the PLL has locked and the frequency has stabilized.
1.8 V power supply
Supports 8 kHz to 200 MHz Single−Ended (LVCMOS) signals. Using PLL Bypass mode,
the output can also be a copy of the input clock. The output will be LOW until the PLL has
locked and the frequency has stabilized.
Table 2. POWER DOWN FUNCTION TABLE
PD# Function
0 Device Powered Down
1 Device Powered Up
TYPICAL CRYSTAL PARAMETERS
Crystal: Fundamental Mode Parallel Resonant
Frequency: 3 MHz to 50 MHz
Table 3. MAX CRYSTAL LOAD CAPACITORS
RECOMMENDATION
Crystal Frequency Range
3 MHz – 30 MHz
Max Cap Value
20 pF
30 MHz – 50 MHz
10 pF
Shunt Capacitance (C0): 7 pF (Max)
Equivalent Series Resistance (ESR): 150 W (Max)
www.onsemi.com
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Номер в каталогеОписаниеПроизводители
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