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NB3H5150-01 PDF даташит

Спецификация NB3H5150-01 изготовлена ​​​​«ON Semiconductor» и имеет функцию, называемую «2.5V / 3.3V Low Noise Multi-Rate Clock Generator».

Детали детали

Номер произв NB3H5150-01
Описание 2.5V / 3.3V Low Noise Multi-Rate Clock Generator
Производители ON Semiconductor
логотип ON Semiconductor логотип 

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NB3H5150-01 Даташит, Описание, Даташиты
NB3H5150-01
2.5V / 3.3V Low Noise
Multi-Rate Clock Generator
Description
The NB3H5150−01 is a high performance Multi−Rate Clock
generator which simultaneously synthesizes up to four different
frequencies from a single PLL using a 25 MHz input reference. The
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reference frequency can be provided by a crystal, LVCMOS/LVTTL,
LVPECL, HCSL or LVDS differential signals. The REFMODE pin
will select the reference source.
MARKING
DIAGRAM*
Three output banks (CLK1A/CLK1B to CLK3A/CLK3B) produce
user selectable frequencies of: 33.33 MHz, 50 MHz, 100 MHz,
125 MHz, or 156.25 MHz and have ultra−low noise/jitter performance
of less than 0.3 ps.
The fourth output bank (CLK4A/CLK4B) can produce the
1 32
1
QFN32
MN SUFFIX
CASE 485CE
NB3H
5150−01
AWLYYWWG
following integer and FRAC−N frequencies in pin−strap mode:
25 MHz, 33.33 MHz, 66.66 MHz, 100 MHz, 125 MHz, 133.33 MHz,
156.25 MHz or 161.1328 MHz.
Each output block can create two single−ended in−phase LVCMOS
outputs or one differential pair of LVPECL outputs.
Each of the four output blocks is independently powered by a
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
separate VDDO, 2.5 V/3.3 V for LVPECL, 1.8 V/2.5 V/3.3 V for
LVCMOS.
The serial (I2C and SMBUS) interface can be used to load register
*For additional marking information, refer to
Application Note AND8002/D.
files into the NB3H5150−01 to program a variety of functions
including the frequencies and output levels of each output which can
ORDERING INFORMATION
be individually enabled and disabled.
See detailed ordering and shipping information on page 18 of
this data sheet.
Features
Flexible Input Reference − 25 MHz Crystal, Oscillator,
1 ps maximum RMS Phase Jitter FRAC−N (CLK4)
Single−Ended or Differential Clock
161.1328 MHz
Four Independent User−Programmable Clock
I2C / SMBus Compatible Interface
Frequencies from 25 MHz to 250 MHz
Independently Configurable Outputs:
Up to Eight LVCMOS Single Ended outputs or,
Up to Four Differential LVPECL Outputs or any
combination of LVCMOS and LVPECL
Flexible Input/Core and Output Power Supply
Combinations:
VDD (Core) = 3.3 V ±5% or 2.5 V ±5%
VDDOn (Outputs) = 3.3 V ±5% or 2.5 V ±5% or
1.8 V ±5% (LVCMOS Only)
Independent Power Supply for each Output Bank
300 ps max Output Rise and Fall Times, LVPECL
1000 ps max Output Rise and Fall Times, LVCMOS
300 fs maximum RMS Phase Jitter Interger−N
(CLK1:4) 156.25 MHz
−40°C to +85°C Ambient Operating Temperature
Zero ppm Multiplication Error
Fractional Divide Ratios for Implementing Arbitrary
FEC/Inverse−FEC Ratios
For Additional Pin−strap Frequency and Output Type
Combinations, Contact ON Semiconductor Sales Office
32−Pin QFN, 5 mm x 5 mm
This is a Pb−Free Device
Applications
Telecom
Networking
Ethernet
SONET
© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 1
1
Publication Order Number:
NB3H5150−01/D









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NB3H5150-01 Даташит, Описание, Даташиты
CLK_XTAL1
CLK_XTAL2
SDA
SCL/PD
MMC
REFMODE
FTM
NB3H5150−01
VDD AVDD1 AVDD2 AVDD3
REF (I2C Mode)
XTAL
OSC
PLL
Integer N
DIV1
Integer N
DIV2
Configuration Table
&
I2C Interface
LDOs
LDO1 LDO2 LDO3 LDO4
Integer N
DIV3
Integer N or
Fractional N
DIV4
VDDO1
CLK1A
CLK1B
VDDO2
CLK2A
CLK2B
VDDO3
CLK3A
CLK3B
VDDO4
CLK4A
CLK4B
Figure 1. Simplified Block Diagram of NB3H5150−01
Exposed Pad (EP)
32 31 30 29 28 27 26 25
CLK_XTAL2 1
24 FTM
REFMODE 2
23 CLK2B
SDA 3
22 CLK2A
SCL/PD 4
VDD 5
NB3H5150−01
21 VDDO2
20 VDDO3
FS1 6
19 CLK3A
FS2 7
18 CLK3B
FS3 8
17 MMC
9 10 11 12 13 14 15 16
Figure 2. 32−Lead QFN Pinout (Top View)
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NB3H5150-01 Даташит, Описание, Даташиты
NB3H5150−01
Table 1. PIN DESCRIPTION
Pin Name
I/O
1 CLK_XTAL2
Crystal or
LVPECL/LVDS
Input
2 REFMODE LVTTL/LVCMOS
Input
3 SDA LVTTL/LVCMOS
Input
4 SCL/PD LVTTL/LVCMOS
Input
5 VDD
6 FS1
7 FS2
8 FS3
9 FS4A
10 FS4B
11 LDO4
12 AVDD3
13 LDO3
14 CLK4A
Power
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Input
Power
Power
Power
Output
15 CLK4B
16 VDDO4
17 MMC
Output
Power
LVTTL/LVCMOS
Input
18 CLK3B
19 CLK3A
Output
Output
20 VDDO3
21 VDDO2
22 CLK2A
Power
Power
Output
23 CLK2B
24 FTM
25 VDDO1
26 CLK1B
27 CLK1A
Output
Power
Output
Output
28 AVDD2
29 LDO2
30 AVDD1
31 LDO1
Power
Power
Power
Power
Description
Crystal Output or Differential Clock Input (complementary); If CLK_XTAL1 is used as
single−ended input, CLK_XTAL2 must be connected to ground. See Table 2.
Reference Input Select to either use a crystal, or overdrive with a single−ended or
differential input; see Table 2. Internal pull−down.
Serial Data Input for I2C/SMBus compatible; Defaults High when left open; internal pull−up.
5V tolerant.
Serial Clock Input for I2C/SMBus compatible; Defaults High when left open; internal
pull−up.
SCL/PD is also a device power−down pin (when High) in pin−strap mode only. 5V tolerant.
3.3 V / 2.5 V Positive Supply Voltage for the Inputs and Core
Frequency Select 1 for DIV1, CLK1A & CLK1B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 3.
Frequency Select 2 for DIV2, CLK2A & CLK2B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 3.
Frequency Select 3 for DIV3, CLK3A, & CLK3B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 3.
Frequency Select 4A for DIV4, CLK4A & CLK4B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 4.
Frequency Select 4B for DIV4, CLK4A & CLK4B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 4.
1.8 V LDO − Install Power Conditioning Bypass Capacitor to Ground
3.3 V / 2.5 V Positive Supply Voltage for Analog circuits. AVDD3 = VDD.
1.8V LDO − Install Power Conditioning Bypass Capacitor to Ground
LVCMOS (single−ended) or Non− Inverted Differential LVPECL Clock A for Channel 4
Output
LVCMOS (single−ended) or Inverted Differential LVPECL Clock B for Channel 4 Output
3.3 V / 2.5 V / 1.8 V Positive Supply Voltage for the CLK4A/4B Outputs
Mix Mode Control Pin for use as a combination of FSn settings and I2C setting for the
CLK(n) outputs in the I2C mode; see Table 6. No logic level default; use a RPull−up resistor
for High or a RPull−down resistor for Low.
LVCMOS (single−ended) or Inverted Differential LVPECL Clock B for Channel 3 Output
LVCMOS (single−ended) or Non−Inverted Differential LVPECL Clock A for Channel 3
Output
3.3 V / 2.5 V / 1.8 V Positive Supply Voltage for the CLK3A/3B Outputs
3.3 V / 2.5 V / 1.8 V Positive Supply Voltage for the CLK2A/2B Outputs
LVCMOS (single−ended) or Non− Inverted Differential LVPECL Clock A for Channel 2
Output
LVCMOS (single−ended) or Inverted Differential LVPECL Clock B for Channel 2 Output
Factory Test Mode. Must connect this pin to Ground.
3.3 V / 2.5 V / 1.8 V Positive Supply Voltage for the CLK1A/1B Outputs
LVCMOS (single−ended) or Inverted Differential LVPECL Clock B for Channel 1 Output
LVCMOS (single−ended) or Non−Inverted Differential LVPECL Clock A for Channel 1
Output
3.3 V / 2.5 V Positive Supply Voltage for Analog circuits. AVDD2 = VDD.
1.8 V LDO − Install Power Conditioning Bypass Capacitor to Ground
3.3 V / 2.5 V Positive Supply Voltage for Analog circuits. AVDD1 = VDD.
1.8 V LDO − Install Power Conditioning Bypass Capacitor to Ground
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ON Semiconductor

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