|
|
PDF 840002I Data sheet ( Hoja de datos )
| Número de pieza | 840002I | |
| Descripción | Crystal-to-LVCMOS/LVTTL Frequency Synthesizer | |
| Fabricantes | IDT | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 840002I (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
|
No Preview Available !
FemtoClocks™ Crystal-to-LVCMOS/
LVTTL Frequency Synthesizer
840002I
DATASHEET
GENERAL DESCRIPTION
The 840002I is a 2 output LVCMOS/LVTTL Synthesizer
optimized to generate Fibre Channel reference clock
frequencies. Using a 26.5625MHz 18pF parallel resonant
crystal, the following frequencies can be generated based on the
2 frequency select pins (F_SEL1:0): 212.5MHz, 159.375MHz,
156.25MHz, 106.25MHz, and 53.125MHz. The 840002I uses
IDT’s 3rd generation low phase noise VCO technology and can
achieve 1ps or lower typical rms phase jitter, easily meeting
Fibre Channel jitter requirements. The 840002I is packaged in
a 16-pin TSSOP package.
FREQUENCY SELECT FUNCTION TABLE
FEATURES
• Two LVCMOS outputs @ 3.3V, 17Ω typical output imped-
ance
• Selectable crystal oscillator interface
or LVCMOS single-ended input
• Output frequency range: 46.66MHz - 233.33MHz
• VCO range: 560MHz - 700MHz
• Supports the following output frequencies: 212.5MHz,
159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz
• RMS phase jitter @ 212.5MHz (637KHz - 10MHz):
0.83ps (typical)
Typical phase noise at 212.5MHz:
Offset
Noise Power
100Hz ................-91.3 dBc/Hz
1KHz ..............-114.3 dBc/Hz
10KHz ..............-120.7 dBc/Hz
100KHz ..............-120.2 dBc/Hz
• Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Lead-Free package RoHS compliant
Input Frequency
(MHz)
F_SEL1
26.5625
0
26.5625
0
26.5625
1
26.5625
1
26.04166
0
BLOCK DIAGRAM
F_SEL0
0
1
0
1
1
Inputs
M Divider Value N Divider Value
24 3
24 4
24 6
24 12
24 4
Output Frequency
M/N Ratio Value
(MHz)
8 212.5
6 159.375
4 106.25
2 53.125
6 156.25
PIN ASSIGNMENT
F_SEL0
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
VDDA
VDD
1
2
3
4
5
6
7
8
16 F_SEL1
15 GND
14 GND
13 Q0
12 Q1
11 VDDO
10 XTAL_IN
9 XTAL_OUT
840002I
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
840002I REVISION A 3/30/15
1 ©2015 Integrated Device Technology, Inc.
1 page  
840002I DATA SHEET
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
F_SEL[1:0] = 00
186.67
fOUT Output Frequency Range
F_SEL[1:0] = 01
F_SEL[1:0] = 10
140
93.33
F_SEL[1:0] = 11
46.67
tsk(o) Output Skew; NOTE 1, 3
212.5MHz @ Integration Range:
637KHz - 10MHz
0.83
159.375MHz @ Integration Range:
637KHz - 10MHz
0.62
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
156.25MHz @ Integration Range:
1.875MHz - 20MHz
0.59
106.25MHz @ Integration Range:
637KHz - 10MHz
0.80
53.125MHz @ Integration Range:
637KHz - 10MHz
0.68
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
F_SEL[1:0] 00
F_SEL[1:0] = 00
200
46
42
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
226.67
170
113.33
56.67
12
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
700 ps
54 %
58 %
TABLE 6B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
F_SEL[1:0] = 00
186.67
fOUT Output Frequency Range
F_SEL[1:0] = 01
F_SEL[1:0] = 10
140
93.33
F_SEL[1:0] = 11
46.67
tsk(o) Output Skew; NOTE 1, 3
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
212.5MHz @ Integration Range:
637KHz - 10MHz
159.375MHz @ Integration Range:
637KHz - 10MHz
156.25MHz @ Integration Range:
1.875MHz - 20MHz
106.25MHz @ Integration Range:
637KHz - 10MHz
53.125MHz @ Integration Range:
637KHz - 10MHz
0.73
0.62
0.56
0.76
0.72
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
F_SEL[1:0] 00
F_SEL[1:0] = 00
200
46
42
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
226.67
170
113.33
56.67
12
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
700 ps
54 %
58 %
REVISION A 3/30/15
5 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
5 Page 
840002I DATA SHEET
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
137.1°C/W
89.0°C/W
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for 840002I is: 3085
REVISION A 3/30/15
11 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet 840002I.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 840002I | Crystal-to-LVCMOS/LVTTL Frequency Synthesizer | IDT |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |