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IS61QDP2B41M36A PDF даташит
| Спецификация IS61QDP2B41M36A изготовлена «ISSI» и имеет функцию, называемую «36Mb QUADP (Burst 4) SYNCHRONOUS SRAM». |
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Детали детали
| Номер произв | IS61QDP2B41M36A |
| Описание | 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM |
| Производители | ISSI |
| логотип |  |
30 Pages
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IS61QDP2B42M18A/A1/A2
IS61QDP2B41M36A/A1/A2
2Mx18, 1Mx36
36Mb QUADP (Burst 4) SYNCHRONOUS SRAM
(2.0 Cycle Read Latency)
JANUARY 2015
FEATURES
1Mx36 and 2Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data
valid window.
Separate independent read and write ports with
concurrent read and write operations.
Synchronous pipeline read with late write operation.
Double Data Rate (DDR) interface for read and
write input ports.
2.0 cycle read latency.
Fixed 4-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control
registering at rising edges only.
Two echo clocks (CQ and CQ#) that are delivered
simultaneously with data.
Data Valid Pin (QVLD).
+1.8V core power supply and 1.5, 1.8V VDDQ, used
with 0.75, 0.9V VREF.
DESCRIPTION
The 36Mb IS61QDP2B41M36A/A1/A2 and
IS61QDP2B42M18A/A1/A2 are synchronous, high-
performance CMOS static random access memory (SRAM)
devices. These SRAMs have separate I/Os, eliminating the
need for high-speed bus turnaround. The rising edge of K
clock initiates the read/write operation, and all internal
operations are self-timed. Refer to the Timing Reference
Diagram for Truth Table for a description of the basic
operations of these QUADP (Burst of 4) SRAMs. Read and
write addresses are registered on alternating rising edges of
the K clock. Reads and writes are performed in double data
rate.
The following are registered internally on the rising edge of
the K clock:
Read/write address
Read enable
Write enable
Byte writes for burst addresses 1 and 3
HSTL input and output interface.
Data-in for burst addresses 1 and 3
Registered addresses, write and read controls, byte
writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1
functions.
Byte write capability.
Fine ball grid array (FBGA) package:
13mmx15mm and 15mmx17mm body size
165-ball (11 x 15) array
Programmable impedance output drivers via 5x
user-supplied precision resistor.
ODT (On Die Termination) feature is supported
optionally on data input, K/K#, and BWx#.
The end of top mark (A/A1/A2) is to define options.
IS61QDP2B41M36A : Don’t care ODT function
and pin connection
IS61QDP2B41M36A1 : Option1
IS61QDP2B41M36A2 : Option2
Refer to more detail description at page 6 for each
The following are registered on the rising edge of the K#
clock:
Byte writes for burst addresses 2 and 4
Data-in for burst addresses 2 and 4
Byte writes can change with the corresponding data-in to
enable or disable writes on a per-byte basis. An internal write
buffer enables the data-ins to be registered one cycle after
the write address. The first data-in burst is clocked one cycle
later than the write command signal, and the second burst is
timed to the following rising edge of the K# clock. Two full
clock cycles are required to complete a write operation.
During the burst read operation, the data-outs from the first
and third bursts are updated from output registers of the third
and fourth rising edges of the K clock (starting 2.0 cycles
later after read command). The data-outs from the second
and fourth bursts are updated with the third and fourth rising
edges of the K# clock where the read command receives at
the first rising edge of K. Two full clock cycles are required to
complete a read operation.
ODT option.
The device is operated with a single +1.8V power supply
and is compatible with HSTL I/O interfaces.
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
12/15/2014
1
No Preview Available ! |
IS61QDP2B42M18A/A1/A2
IS61QDP2B41M36A/A1/A2
Package ballout and description
x36 FBGA Ball ballout (Top View)
1234
A CQ# NC/SA1 NC/SA1 W#
B Q27 Q18 D18
SA
C D27 Q28 D19 VSS
D D28 D20 Q19 VSS
E
Q29
D29
Q20
VDDQ
F
Q30
Q21
D21
VDDQ
G
D30
D22
Q22
VDDQ
H Doff#
VREF
VDDQ
VDDQ
J
D31
Q31
D23
VDDQ
K
Q32
D32
Q23
VDDQ
L
Q33
Q24
D24
VDDQ
M D33 Q34 D25 VSS
N D34 D26 Q25 VSS
P Q35 D35 Q26
SA
R TDO TCK
SA
SA
5
BW2#
BW3#
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
SA
6
K#
K
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
QVLD
ODT
7
BW1#
BW0#
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
SA
8
R#
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
SA
9
SA
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
SA
10
NC/SA1
Q17
Q7
D15
D6
Q14
D13
VREF
Q4
D3
Q11
Q1
D9
D0
TMS
The following balls are reserved for higher densities: 3A for 72Mb, 10A for 144Mb, and 2A for 288Mb.
x18 FBGA Ball ballout (Top View)
123
A CQ# NC/SA1 SA
45678
W# BW1# K# NC/SA1 R#
9
SA
B NC Q9 D9 SA NC
K
BW0#
SA
NC
C NC NC D10 VSS SA NC SA VSS NC
D NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
E NC
NC
Q11
VDDQ
VSS
VSS
VSS VDDQ NC
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
H Doff# VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
K NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS VDDQ NC
M NC NC D16 VSS VSS VSS VSS VSS NC
N NC D17 Q16 VSS SA SA SA VSS NC
P NC NC Q17 SA SA QVLD SA SA NC
R TDO TCK
SA
SA
SA ODT SA
SA
SA
Notes:
1. The following balls are reserved for higher densities: 10A for 72Mb, 2A for 144Mb, and 7A for 288Mb.
10
NC/SA1
NC
Q7
NC
D6
NC
NC
VREF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
12/15/2014
2
No Preview Available ! |
IS61QDP2B42M18A/A1/A2
IS61QDP2B41M36A/A1/A2
Ball Description
Symbol
K, K#
CQ, CQ#
Doff#
QVLD
SA
D0 - Dn
Q0 - Qn
W#
R#
BWx#
VREF
VDD
VDDQ
VSS
ZQ
TMS, TDI,
TCK
TDO
NC
ODT
Type
Input
Output
Input
Output
Input
Input
Output
Input
Input
Input
Input
reference
Power
Power
Description
Input clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges.
These balls cannot remain VREF level.
Synchronous echo clock outputs: The edges of these outputs are tightly matched to the
synchronous data outputs and can be used as a data valid indication. These signals are free running
clocks and do not stop when Q tri-states.
DLL disable and reset input : when low, this input causes the DLL to be bypassed and reset the
previous DLL information. When high, DLL will start operating and lock the frequency after tCK lock
time. The device behaves in one read latency mode when the DLL is turned off. In this mode, the
device can be operated at a frequency of up to 167 MHz.
Valid output indicator: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and
CQ#.
Synchronous address inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. These inputs are ignored when device is deselected.
Synchronous data inputs: Input data must meet setup and hold times around the rising edges of K
and K# during WRITE operations. See BALL CONFIGURATION figures for ball site location of
individual signals.
The x18 device uses D0~D17. D18~D35 should be treated as NC pin.
The x36 device uses D0~D35.
Synchronous data outputs: Output data is synchronized to the respective CQ and CQ#, or to the
respective K and K# if C and /C are tied to high. This bus operates in response to R# commands.
See BALL CONFIGURATION figures for ball site location of individual signals.
The x18 device uses Q0~Q17. Q18~Q35 should be treated as NC pin.
The x36 device uses Q0~Q35.
Synchronous write: When low, this input causes the address inputs to be registered and a WRITE
cycle to be initiated. This input must meet setup and hold times around the rising edge of K.
Synchronous read: When low, this input causes the address inputs to be registered and a READ
cycle to be initiated. This input must meet setup and hold times around the rising edge of K.
Synchronous byte writes: When low, these inputs cause their respective byte to be registered and
written during WRITE cycles. These signals are sampled on the same edge as the corresponding
data and must meet setup and hold times around the rising edges of K and #K for each of the two
rising edges comprising the WRITE cycle. See Write Truth Table for signal to data relationship.
HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise
margin. Provides a reference voltage for the HSTL input buffers.
Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range.
Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating
Conditions for range.
Ground Ground of the device
Input
Output impedance matching input: This input is used to tune the device outputs to the system data
bus impedance. Q and CQ output impedance are set to 0.2xRQ, where RQ is a resistor from this
ball to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance
mode. This ball cannot be connected directly to VSS or left unconnected.
In ODT (On Die Termination) enable devices, the ODT termination values tracks the value of RQ.
The ODT range is selected by ODT control input.
Input
IEEE1149.1 input pins for JTAG.
Output
N/A
Input
IEEE1149.1 output pins for JTAG.
No connect: These signals should be left floating or connected to ground to improve package heat
dissipation.
ODT control; Refer to SRAM features for the details.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
12/15/2014
3
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