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PDF NCT6106D Data sheet ( Hoja de datos )

Número de pieza NCT6106D
Descripción LPC I/O
Fabricantes novoTon　
Logotipo novoTon Logotipo



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No Preview Available ! NCT6106D Hoja de datos, Descripción, Manual

NCT6102D / NCT6106D
Nuvoton LPC I/O
Date: January 11th, 2012 Revision 1.0

1 page




NCT6106D pdf
NCT6102D / NCT6106D
9.38
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PCH_TSI3_TEMP_H Register – Index 5Fh (Bank 0) ..................................................................... 96
PCH_TSI3_TEMP_L Register – Index 60h (Bank 0) ...................................................................... 97
PCH_TSI4_TEMP_H Register – Index 61h (Bank 0) ..................................................................... 97
PCH_TSI4_TEMP_L Register – Index 62h (Bank 0) ...................................................................... 97
PCH_TSI5_TEMP_H Register – Index 63h (Bank 0) ..................................................................... 98
PCH_TSI5_TEMP_L Register – Index 64h (Bank 0) ...................................................................... 98
PCH_TSI6_TEMP_H Register – Index 65h (Bank 0) ..................................................................... 98
PCH_TSI6_TEMP_L Register – Index 66h (Bank 0) ...................................................................... 98
PCH_TSI7_TEMP_H Register – Index 67h (Bank 0) ..................................................................... 99
PCH_TSI7_TEMP_L Register – Index 68h (Bank 0) ...................................................................... 99
ByteTemp_H Register – Index 69h (Bank 0) .................................................................................. 99
ByteTemp_L Register – Index 6Ah (Bank 0) .................................................................................. 99
Peci Temp Register – Index 6Bh (Bank 0).................................................................................... 100
Interrupt Status Register 1 – Index 70h (Bank 0).......................................................................... 100
Interrupt Status Register 2 – Index 71h (Bank 0).......................................................................... 100
Interrupt Status Register 3 – Index 72h (Bank 0).......................................................................... 101
Interrupt Status Register 4 – Index 73h (Bank 0).......................................................................... 102
Interrupt Status Register 5 – Index 74h (Bank 0).......................................................................... 102
Interrupt Status Register 6 – Index 75h (Bank 0).......................................................................... 103
Interrupt Status Register 7 – Index 76h (Bank 0).......................................................................... 103
Real Time Status Register 1 – Index 77h (Bank 0)....................................................................... 103
Real Time Status Register 2 – Index 78h (Bank 0)....................................................................... 104
Real Time Status Register 3 – Index 79h (Bank 0)....................................................................... 105
Real Time Status Register 4 – Index 7Ah (Bank 0) ...................................................................... 105
Real Time Status Register 5 – Index 7Bh (Bank 0) ...................................................................... 106
Real Time Status Register 6 – Index 7Ch (Bank 0) ...................................................................... 107
Real Time Status Register 7 – Index 7Dh (Bank 0) ...................................................................... 107
Reserved Register – Index 7Eh ~ 7Fh (Bank 0) ........................................................................... 108
SMI# Mask Register 1 – Index 80h (Bank 0) ................................................................................ 108
SMI# Mask Register 2 – Index 81h (Bank 0) ................................................................................ 108
SMI# Mask Register 3 – Index 82h (Bank 0) ................................................................................ 109
SMI# Mask Register 4 – Index 83h (Bank 0) ................................................................................ 109
SMI# Mask Register 5 – Index 84h (Bank 0) ................................................................................ 110
SMI# Mask Register 6 – Index 85h (Bank 0) ................................................................................ 110
SMI# Mask Register 7 – Index 86h (Bank 0) ................................................................................ 111
CPUVCORE High Limit Voltage Register – Index 90h (Bank 0) .................................................. 111
CPUVCORE Low Limit Voltage Register – Index 91h (Bank 0) ................................................... 111
VIN0 High Limit Voltage Register – Index 92h (Bank 0) ............................................................... 112
VIN1 Low Limit Voltage Register – Index 93h (Bank 0)................................................................ 112
AVCC High Limit Voltage Register – Index 94h (Bank 0) ............................................................. 112
AVCC Low Limit Voltage Register – Index 95h (Bank 0).............................................................. 112
3VCC High Limit Voltage Register – Index 96h (Bank 0) ............................................................. 113
3VCC Low Limit Voltage Register – Index 97h (Bank 0) .............................................................. 113
VIN1 High Limit Voltage Register – Index 98h (Bank 0) ............................................................... 113
VIN1 Low Limit Voltage Register – Index 99h (Bank 0)................................................................ 113
VIN2 High Limit Voltage Register – Index 9Ah (Bank 0)............................................................... 114
Publication Release Date: January 11, 2012
-IV- version: 1.0

5 Page





NCT6106D arduino
NCT6102D / NCT6106D
10.1 FDC Functional Description .......................................................................................................... 192
10.1.1 FIFO (Data) ............................................................................................................................. 192
10.1.2 Data Separator ........................................................................................................................ 193
10.1.3 Write Precompensation ........................................................................................................... 193
10.1.4 Perpendicular Recording Mode ............................................................................................... 193
10.1.5 FDC Core ................................................................................................................................ 193
10.1.6 FDC Commands...................................................................................................................... 194
10.2 Register Descriptions .................................................................................................................... 202
10.2.1 Status Register A (SA Register) (Read base address + 0)..................................................... 202
10.2.2 Status Register B (SB Register) (Read base address + 1) ..................................................... 203
10.2.3 Digital Output Register (DO Register) (Write base address + 2) ............................................ 204
10.2.4 Tape Drive Register (TD Register) (Read base address + 3) ................................................. 204
10.2.5 Main Status Register (MS Register) (Read base address + 4)............................................... 205
10.2.6 Data Rate Register (DR Register) (Write base address + 4) .................................................. 206
10.2.7 FIFO Register (R/W base address + 5)................................................................................... 207
10.2.8 Digital Input Register (DI Register) (Read base address + 7)................................................. 210
10.2.9 Configuration Control Register (CC Register) (Write base address + 7) ................................ 211
11. UART PORT .................................................................................................................................. ........... 212
11.1 UART Control Register (UCR) (Read/Write)................................................................................. 212
11.2 UART Status Register (USR) (Read/Write) .................................................................................. 214
11.3 Handshake Control Register (HCR) (Read/Write) ........................................................................ 214
11.4 Handshake Status Register (HSR) (Read/Write).......................................................................... 215
11.5 UART FIFO Control Register (UFR) (Write only) .......................................................................... 216
11.6 Interrupt Status Register (ISR) (Read only) .................................................................................. 216
11.7 Interrupt Control Register (ICR) (Read/Write)............................................................................... 217
11.8 Programmable Baud Generator (BLL/BHL) (Read/Write)............................................................. 218
11.9 User-defined Register (UDR) (Read/Write)................................................................................... 219
11.10 Extendding FIFO ........................................................................................................................... 219
11.11 UART RS485 Auto Flow Control................................................................................................... 219
11.12 UART 9BIT-MODE ........................................................................................................................ 220
11.12.1 Function Dscription.................................................................................................................. 220
11.12.2 Function Block ......................................................................................................................... 223
12. PARALLEL PORT.......................................................................................................................... ........... 225
12.1 Printer Interface Logic ................................................................................................................... 225
12.2 Enhanced Parallel Port (EPP) ....................................................................................................... 226
12.2.1 Data Port (Data Swapper) ....................................................................................................... 226
12.2.2 Printer Status Buffer ................................................................................................................ 227
12.2.3 Printer Control Latch and Printer Control Swapper ................................................................. 227
12.2.4 EPP Address Port.................................................................................................................... 228
12.2.5 EPP Data Port 0-3 ................................................................................................................... 228
12.2.6 EPP Pin Descriptions .............................................................................................................. 228
12.2.7 EPP Operation......................................................................................................................... 229
12.2.8 EPP Version 1.9 Operation ..................................................................................................... 229
12.2.9 EPP Version 1.7 Operation ..................................................................................................... 229
12.3 Extended Capabilities Parallel (ECP) Port .................................................................................... 229
Publication Release Date: January 11, 2012
-X- version: 1.0

11 Page







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