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AD5668 - Analog Devices - SPI Voltage Output denseDAC

Номер произв AD5668
Описание SPI Voltage Output denseDAC
Производители Analog Devices
логотип Analog Devices логотип 
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AD5668 Даташит, Описание, Даташиты
Data Sheet
Octal, 12-/14-/16-Bit SPI Voltage Output
denseDAC with 5 ppm/°C On-Chip Reference
AD5628/AD5648/AD5668
FEATURES
Low power, small footprint, pin-compatible octal DACs
AD5668: 16 bits
AD5648: 14 bits
AD5628: 12 bits
14-lead/16-lead TSSOP, 16-lead LFCSP, and 16-lead WLCSP
On-chip 1.25 V/2.5 V, 5 ppm/°C reference
Power down to 400 nA at 5 V, 200 nA at 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale or midscale
3 power-down functions
Hardware LDAC and LDAC override function
CLR function to programmable code
Rail-to-rail operation
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5628/AD5648/AD5668 devices are low power, octal,
12-/14-/16-bit, buffered voltage-output DACs. All devices
operate from a single 2.7 V to 5.5 V supply and are guaranteed
monotonic by design. The AD5668 and AD5628 are available in
both a 4 mm × 4 mm LFCSP and a 16-lead TSSOP, while the
AD5648 is available in both a 14-lead and 16-lead TSSOP.
The AD5628/AD5648/AD5668 have an on-chip reference with
an internal gain of 2. The AD5628-1/AD5648-1/AD5668-1 have
a 1.25 V 5 ppm/°C reference, giving a full-scale output range
of 2.5 V; the AD5628-2/AD5648-2/AD5668-2 and AD5668-3 have
a 2.5 V 5 ppm/°C reference, giving a full-scale output range of
5 V. The on-board reference is off at power-up, allowing the use
of an external reference. The internal reference is enabled via a
software write.
The part incorporates a power-on reset circuit that ensures that the
DAC output powers up to 0 V (AD5628-1/AD5648-1/AD5668-1,
AD5628-2/AD5648-2/AD5668-2) or midscale (AD5668-3) and
remains powered up at this level until a valid write takes place.
The part contains a power-down feature that reduces the current
consumption of the device to 400 nA at 5 V and provides software-
Rev. I
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
SCLK
SYNC
DIN
VDD
AD5628/AD5648/AD5668
LDAC
INTERFACE
LOGIC
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
POWER-ON
RESET
VREFIN/VREFOUT
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
1.25V/2.5V
REF
STRING
DAC A
BUFFER
STRING
DAC B
BUFFER
STRING
DAC C
BUFFER
STRING
DAC D
BUFFER
STRING
DAC E
BUFFER
STRING
DAC F
BUFFER
STRING
DAC G
BUFFER
STRING
DAC H
BUFFER
POWER-DOWN
LOGIC
LDAC1 CLR1
1RU-16 AND WLCSP PACKAGE ONLY.
Figure 1.
GND
VOUTA
VOUTB
VOUTC
VOUTD
VOUTE
VOUTF
VOUTG
VOUTH
selectable output loads while in power-down mode for any or all
DAC channels. The outputs of all DACs can be updated simul-
taneously using the LDAC function, with the added functionality
of user-selectable DAC channels to simultaneously update. There
is also an asynchronous CLR that updates all DACs to a user-
programmable code—zero scale, midscale, or full scale.
The AD5628/AD5648/AD5668 utilize a versatile 3-wire serial
interface that operates at clock rates of up to 50 MHz and is
compatible with standard SPI®, QSPI™, MICROWIRE™, and
DSP interface standards. The on-chip precision output amplifier
enables rail-to-rail output swing.
PRODUCT HIGHLIGHTS
1. Octal, 12-/14-/16-bit DAC.
2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.
3. Available in 14-lead/16-lead TSSOP, 16-lead LFCSP, and
16-lead WLCSP.
4. Power-on reset to 0 V or midscale.
5. Power-down capability. When powered down, the DAC
typically consumes 200 nA at 3 V and 400 nA at 5 V.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2005–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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AD5668 Даташит, Описание, Даташиты
AD5628/AD5648/AD5668
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 6
Timing Characteristics ................................................................ 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 19
Theory of Operation ...................................................................... 21
REVISION HISTORY
11/14—Rev. H to Rev. I
Changes to Ordering Guide .......................................................... 29
2/14—Rev. G to Rev. H
Changes to Figure 1.......................................................................... 1
Change to Figure 6 ......................................................................... 10
Change to Table 7 ........................................................................... 10
Changes to Figure 45, Figure 46, and Figure 47 ......................... 17
Changes to Ordering Guide .......................................................... 29
1/13—Rev. F to Rev. G
Added WLCSP Reference TC of 15 ppm/°C, Table 2 .................. 5
Changes to Ordering Guide .......................................................... 29
8/11—Rev. E to Rev. F
Added 16-Lead WLCSP.....................................................Universal
Added Figure 6 and Table 7; Renumbered Sequentially ........... 10
Changes to Figure 32 and Figure 33............................................. 15
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 28
1/11—Rev. D to Rev. E
Changes to AD5628 Relative Accuracy, Zero-Code Error, Offset
Error, and Reference TC Parameters, Table 1............................... 3
Changes to AD5628 Relative Accuracy, Zero-Code Error, Offset
Error, and Reference TC Parameters, Table 2............................... 5
Changes to Output Voltage Settling Time, Table 3 ...................... 6
Added Figure 53; Renumbered Sequentially .............................. 17
Change to Output Amplifier Section........................................... 21
Changes to Ordering Guide .......................................................... 28
Data Sheet
D/A Section................................................................................. 21
Resistor String............................................................................. 21
Internal Reference ...................................................................... 21
Output Amplifier........................................................................ 22
Serial Interface ............................................................................ 22
Input Shift Register .................................................................... 23
SYNC Interrupt .......................................................................... 23
Internal Reference Register....................................................... 24
Power-On Reset.......................................................................... 24
Power-Down Modes .................................................................. 24
Clear Code Register ................................................................... 24
LDAC Function .......................................................................... 26
Power Supply Bypassing and Grounding................................ 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 29
9/10—Rev. C to Rev. D
Change to Title...................................................................................1
Added 16-Lead LFCSP Throughout ................................Universal
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................5
Changes to Table 3.............................................................................6
Changes to Table 4.............................................................................7
Deleted SnPb from Table 5...............................................................8
Added Figure 5; Renumbered Sequentially ...................................9
Changes to Table 6.............................................................................9
Replaced Typical Performance Characteristics Section ............ 10
Changes to Power-On Reset Section ........................................... 23
Updated Outline Dimensions....................................................... 26
Changes to Ordering Guide .......................................................... 28
1/10—Rev. B to Rev. C
Changes to Figure 3........................................................................ 10
Changes to Ordering Guide .......................................................... 28
2/09—Rev. A to Rev. B
Changes to Reference Current Parameter, Table 1........................3
Changes to IDD (Normal Mode) Parameter, Table 1......................4
Changes to Reference Current Parameter, Table 2........................5
Changes to IDD (Normal Mode) Parameter, Table 2......................6
11/05—Rev. 0 to Rev. A
Change to Specifications ..................................................................3
10/05—Revision 0: Initial Version
Rev. I | Page 2 of 29
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AD5668 Даташит, Описание, Даташиты
Data Sheet
AD5628/AD5648/AD5668
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
A Grade1
B Grade1
Min Typ Max Min Typ Max Unit
Conditions/Comments
STATIC PERFORMANCE2
AD5628
Resolution
Relative Accuracy
Differential Nonlinearity
AD5648
Resolution
12 12 Bits
±0.5 ±4
±0.5 ±1 LSB
±0.25
±0.25 LSB
14 14 Bits
See Figure 9
Guaranteed monotonic by design
(see Figure 12)
Relative Accuracy
Differential Nonlinearity
±2 ±8
±0.5
±2 ±4 LSB
±0.5 LSB
See Figure 8
Guaranteed monotonic by design
(see Figure 11)
AD5668
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Zero-Code Error Drift
Full-Scale Error
Gain Error
Gain Temperature Coefficient
16 16 Bits
±8 ±32
±8 ±16 LSB
See Figure 7
±1
±1 LSB
Guaranteed monotonic by design
(see Figure 10)
6 19
6 19 mV
All 0s loaded to DAC register (see Figure 26)
±2 ±2 µV/°C
−0.2 −1
−0.2 −1
% FSR All 1s loaded to DAC register
(see Figure 27)
±1 ±1 % FSR
±2.5 ±2.5 ppm Of FSR/°C
Offset Error
DC Power Supply Rejection Ratio
DC Crosstalk
(External Reference)
DC Crosstalk
(Internal Reference)
±6 ±19
–80
10
5
10
25
10
±6 ±19
–80
10
5
10
25
10
mV
dB
µV
µV/mA
µV
µV
µV/mA
VDD ± 10%
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
OUTPUT CHARACTERISTICS3
Output Voltage Range
Capacitive Load Stability
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE INPUTS
0 VDD 0 VDD V
2 2 nF RL = ∞
10 10 nF RL = 2 kΩ
0.5 0.5 Ω
30 30 mA VDD = 5 V
4 4 µs Coming out of power-down mode, VDD = 5 V
Reference Current
Reference Input Range
Reference Input Impedance
40 55
40 55
µA
0 VDD 0 VDD V
14.6 14.6 kΩ
VREF = VDD = 5.5 V (per DAC channel)
REFERENCE OUTPUT
Output Voltage
AD56x8-2, AD56x8-3
Reference TC3
2.495
5
2.505 2.495
10 5
2.505 V
At ambient
10 ppm/°C TSSOP
Reference Output Impedance
15
7.5
5 10
7.5
ppm/°C LFCSP
kΩ
Rev. I | Page 3 of 29
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